UNIDADE 3
exemplos de construções de linhas de comandosde alguns projetos práticos em VHDL
http://vhdl.com.br/site/exemplos
https://www.tutorialspoint.com/vlsi_design/vhdl_programming_for_combinational_circuits.htm
--Conversor Digital-Analógico
IEEE;
IEEE .STO LOGIC_1164 .ALL;
ieee.num.er ic_std .all;
OAC is
Por t (
"CLK, RST, STARl'"
"01, 02, CLI<_OUT, n SYNC OATA1, OATA2"
std_logicll downto 0) ) ;
OAC;
out std_logic;
· in std_logic;
- in
Behavio ral of DAC is
"states is ( Idle,Shif tOut ,SyncData ) ;"
"cu rrent_staU!
next_state" "states;
- states;"
downto 0) ; "ten;pl , ten;p2
1" · std_logic_vec:tor (15
"clk_div , shif tCoun U!r," "enShif tCounter , enParalelLoad"
std_logic ;
": p rocess ( clk, rst )"
clk_counter in teger range O to 5; --f or 120MHz system clock . 12 0/S = 24MHz serial clock .
",it (r ising_edge ( clk ) ) then"
",it C rst = '1' ) tr.f!n"
clk_div <= • O ' ;
clk_out <= • o ·;
clk= O ;
il (clk_counter = 5) then
clk_div <= ' 1' ; clk_out <= ' 1' ;
clk = O ;
clk_div <= ' o·;
clk_out <= ' o ·;
clk= clk counter + 1;
process;
if ;
if ;
if ;
OATA2 )
"pr ocess ( clk_div , shif tcoun te r, enParale lLoad, enShif tCounter, DATA1,"
count : integer range O to 15;
",it ( r ising_edge ( clk_div )) then"
",it (enPar alelLoad = '1' ) then"
"<= 'O ' ; templ <= ""0000 "" & OATA1; temp2 <= ""0000 "" & OATA2 ;"
( enShiftCoun U!r = ' 1' ) then
templ <= 14 downto 0) &temp1( 15 ) ;
temp2 <= 14 downto 0) &temp2 ( 15 ) ;
:= count + 1;
",it (count = 15) then"
process;
if ;
if ;
if ;
<= '1' ;
01 <= 15 ) ;
02 <= 15 ) ;
"SYNC_PROC : process ( clk_div , rst )"
il (rising_edge ( clk_div ) ) then
JJ (r st = '1' ) then
current state <= Idle;
current staU! <= next_state;
if ;
if ; process;
"OUT PUT DEOOOE: process (CLI<, current_state )"
il (r ising_e dge (CLK) ) then
",it (current_state = Idle) then"
<= ' O ' ;
DONE <= '1 ' ;
<=' 1' ;
<= ' 1' ;
( current_state = Shif tOut ) then
<=' 1' ;
DONE <= ' O ' ;
<= ' 0 ' ;
<= ' O ' ;
process;
if ;
if ;
DONE <= 'O ' ;
<=' 1' ;
<= ' O ' ;
<= ' O ' ;
"NEXT STATE OECODE: process (CLI<, cur rent_sta te, STARl', shiftCoun U!r )"
",it (r ising_edge (CLK) ) then"
next state <= cu rren t_state ; (current_state ) is
Idle =>
",it (STARI = '1' ) then"
next state <= Shif tOut;
if ;
Shif tOu t =>
il (shiftCounter = • 1• ) then
next state <= SyncData;
if ;
SyncData =>
",it (STARI = ' O ' ) then"
next state <= Idle ;
if ;
case;
if ;
others =>
next state <= Idle;
Gerador de número aleatório em VHDL
Código:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity random is
generic ( width : integer := 32 );
port (
clk : in std_logic;
random_num : out std_logic_vector (width-1 downto 0) --output vector
);
end random;
architecture Behavioral of random is
begin
process(clk)
variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0');
variable temp : std_logic := '0';
begin
if(rising_edge(clk)) then
temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;
end if;
random_num <= rand_temp;
end process;
end Behavioral;
Testbench em VHDL:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
--Input and Output definitions.
signal clk : std_logic := '0';
signal random_num : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.random generic map (width => 4) PORT MAP (
clk => clk,
random_num => random_num
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
END behavior;
http://vhdl.com.br/site/exemplos/154-gerador-de-n%C3%BAmero-aleat%C3%B3rio-em-vhdl
Relógio Digital
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity digi_clk is
port (
clk1 : in std_logic;
seconds : out std_logic_vector(5 downto 0);
minutes : out std_logic_vector(5 downto 0);
hours : out std_logic_vector(4 downto 0)
);
end digi_clk;
architecture Behavioral of digi_clk is
signal sec,min,hour : integer range 0 to 60 :=0;
signal count : integer :=1;
signal clk : std_logic :='0';
begin
seconds <= conv_std_logic_vector(sec,6);
minutes <= conv_std_logic_vector(min,6);
hours <= conv_std_logic_vector(hour,5);
--clk generation.For 100 MHz clock this generates 1 Hz clock.
process(clk1)
begin
if(clk1'event and clk1='1') then
count <=count+1;
if(count = 50000000) then
clk <= not clk;
count <=1;
end if;
end if;
end process;
process(clk) --period of clk is 1 second.
begin
if(clk'event and clk='1') then
sec <= sec+ 1;
if(sec = 59) then
sec<=0;
min <= min + 1;
if(min = 59) then
hour <= hour + 1;
min <= 0;
if(hour = 23) then
hour <= 0;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
http://vhdl.com.br/site/exemplos/143-rel%C3%B3gio-digital-em-vhdl